FPGA · certified sparse FFT
Certified exactness on FPGA — sparse when provable, with a certified dense fallback.
What it is
Core is a family of deterministic sparse FFT engines wrapped in a per-frame certification layer with a dense radix-2 fallback within its supported frame sizes. Unlike probabilistic sparse FFTs, which can silently miss components, Core’s system output is certified correct across each engine’s supported range: the certification layer decides — per frame — which route is authoritative, and on any failure it routes to the dense path, which stays authoritative within its supported frame sizes. Evidence is simulation (iverilog) + Quartus fit/STA + post-fit power; there is no board bring-up yet, and power confidence is Medium.
By the numbers
Measured · sim + post-fit (no board)Architecture
Multiple compute routes, one certification and fallback contract
Each sparse engine claims only its measured envelope; the dense radix-2 path is the correctness backstop within its supported frame sizes, and the certification layer decides — per frame — which route’s output is authoritative.
Primary sparse route
The primary sparse compute route, timing-closed at 98.38 MHz on Cyclone V (+0.144 ns worst setup slack), with 759.92 mW full-frame post-fit power at Medium confidence.
Low-k native route
A native low-k detection route. Bounded claim at N=65536, k ≤ 25 on real-world payloads: 16/16 exact with 0 false positives, within 34.7% of the dense cycle budget.
Large-N route
A subsampled detection route with exact per-bin verification for large N. At N=262144: 33/33 exact, 0 false positives, bit-identical. Synthesizable — fits the target Cyclone V FPGA at 35.21 MHz.
Dense radix-2 fallback
A deterministic dense FFT that is authoritative whenever certification fails, within its supported frame sizes. Deterministically correct for N ≤ 65536; 44 MHz timing closes on 1 of 3 seeds (single-seed-marginal).
Per-frame certification layer
Per-frame certification metrics gate every sparse result. When a metric fails, the system fails closed and routes to the dense path — by design, a silent miss cannot become the system output.
How measured
How the result is measured
Every number on this page traces to a committed artifact. Five measurement pillars back the claims; anything not backed by an artifact is not claimed.
Native parity
iverilog -g2012 simulation parity: detected bins are bit-identical to per-frame truth across each engine’s measured envelope.
Timing
Quartus Prime fit + STA: slow-corner restricted Fmax, multi-seed sweeps. Timing claims quote the worst setup slack of the promoted seed.
Power
Gate-level toggle capture → Quartus Power Analyzer, at Medium confidence; the power netlist sha256 is matched to the timing evidence.
Fail-closed gate
An evidence gate with pinned regression signatures, artifact freshness + sha256 provenance checks, and a unit-test suite. A stale or missing artifact fails the gate.
Claim ledger
Every claim is tagged measured / bounded / pending in a maintained claim ledger, so the claim status is always inspectable.
Where it works
Where it runs sparse, and where it falls back
Claims are scoped per engine and per regime. Sparse claims exist only inside measured envelopes; everywhere else, certification fails closed and the dense path is authoritative.
| Regime | Status | Path | Claim |
|---|---|---|---|
| Primary sparse route | MEASURED | sparse + cert | 98.38 MHz closed; full-frame 759.92 mW Medium |
| Low-k native route (N=65536, k≤25), real-world payloads | BOUNDED | native sparse | 16/16 exact, 0 false positives; within 34.7% of dense cycle budget |
| Low-k route outside envelope (clustered payloads, k>25) | OPEN | dense fallback | certification fails closed → dense authoritative |
| Large-N route (N=262144), real + synthetic k∈{5,15,25} | BOUNDED | native sparse | 33/33/0 bit-identical; synthesizable on the target Cyclone V at 35.21 MHz |
| Large-N route, out-of-envelope real payloads | OPEN (measured boundary) | fail closed | non-exact natively — reported, not concealed; no local dense at this N |
| Dense fallback, N ≤ 65536 | MEASURED | dense | deterministically correct; 44 MHz on 1-of-3 seeds; 418.87 mW Medium over a partial frame window |
| Dense, N=131072 | DEVICE LIMIT | — | exceeds the target FPGA on-chip memory capacity (first-fail 3/3 seeds) |
Application fit
Why this matters beyond the FFT
Application fit and platform relevance, not measured proof. The measured claims are the envelope rows above and the committed evidence artifacts behind them.
Guarantee class
Deterministic + certified versus probabilistic. Published faster sparse FFTs can silently miss components; within its certified envelope, Core’s output does not — every returned result is verified per frame.
Defense / radar / EW / SIGINT edge
Edge fit for radar, EW, and SIGINT payloads on FPGA: timing, power, and resource-fit SWaP numbers are now measurable on Cyclone V-class parts.
Evidence discipline as product
A fail-closed evidence gate — pinned regression signatures, artifact freshness, sha256 provenance — makes the evidence base diligence-survivable.
NVIDIA review
The FPGA lane of the SparseTech portfolio
This is the FPGA lane; it makes no CUDA performance claim. What can be evaluated here is the evidence chain (rerun the fail-closed buyer-readiness gate against the sha256-provenanced artifacts), the certification contract, and how Core pairs with the SparseDSP CUDA lane — Vector and Relay — as the same deterministic certification concept measured on both substrates.
Guardrails
Not claimed
- Not unconditionally production-ready — the gate lists measured bounded claims by design.
- Not exact outside each engine’s measured envelope.
- Not silicon-validated — evidence is simulation + fit/STA + post-fit power; no board bring-up yet.
- Not a dense-FFT throughput win vs vendor IP.
- Not 50 MHz on the large-N native core (35.21 MHz; pipelining pending).
- Not multi-seed-robust dense timing (44 MHz closes 1 of 3 seeds).
- Not full-frame dense energy (partial-frame window; hardware-limited).
- Not High-confidence power (Medium, moderately complete toggle data).
- Dense fallback stays authoritative whenever certification fails, within its supported frame sizes.
Sparse when provable, certified-correct in-envelope.
See how the same certification discipline runs on the GPU lane — or request an evaluation packet.
NVIDIA and CUDA are trademarks and/or registered trademarks of NVIDIA Corporation. Cyclone V and Quartus Prime are trademarks of their respective owner; iverilog is an open-source project. References to third-party tools and devices describe the measured environment and do not imply endorsement.