SparseDSP
A portfolio of certified sparse-output engines across GPU and FPGA. Vector computes only the k significant components on the GPU and Relay certifies the result; Discovery reduces a corpus to a verified candidate set and serves an open LLM; Core brings certified-exact sparse FFT to FPGA. One discipline throughout: certified results where the sparse path is provable, and a safe, authoritative fallback everywhere else.
The portfolio
Every product emits a verified result inside its stated envelope, and fails closed to a safe, authoritative path outside it — dense where the device supports it. The substrate changes — CUDA GPU, verifiable LLM serving, FPGA — the discipline does not.

A CUDA sparse FFT (cuSFFT) that computes only the k components that matter.
Explore Vector →
The runtime that certifies Vector’s output and guarantees a dense fallback.
Explore Relay →
Reduce a large corpus to a small, verified candidate set — then serve an open LLM behind provenance-carrying, fail-closed contracts.
Explore Discovery →
Certified exactness on FPGA — sparse when provable, with a certified dense fallback.
Explore Core →CUDA sparse-FFT lane · Vector + Relay
cuSFFT · device-residentMeasured against a dense cuFFT + top-k baseline, in the supported range. Outside it, Relay routes to the dense path and dense cuFFT stays authoritative. Discovery and Core carry their own measured numbers on their pages.
Measured on NVIDIA
The SparseDSP GPU lanes are measured on NVIDIA RTX 5070 Ti and GB10 / Spark — Vector and Relay head-to-head against a fair pinned dense cuFFT baseline, Discovery on a single-GPU vLLM serving lane. Core is the FPGA lane. SparseTech is a member of the NVIDIA Inception program.
NVIDIA, CUDA, cuFFT, GB10, RTX, and Inception are trademarks and/or registered trademarks of NVIDIA Corporation. NVIDIA Inception is a startup-enablement program; membership does not constitute NVIDIA endorsement of these results or claims.